1. Field of the Invention
The present invention relates to a semiconductor memory device which includes a sense amplifier circuit connected to a memory cell via a sense line, a sense amplifier circuit suitable for reading the memory cell of the semiconductor memory device, and a memory cell reading method.
2. Description of the Related Art
In semiconductor memory devices, the magnitude of a cell current varies depending on the storage status of a memory cell. Stored data associated with the magnitude of the cell current is read. Recent years have seen progress in nonvolatile memory development.
Well known among two-terminal variable resistance type nonvolatile memories is spin injection memory (refer to Japanese Patent Laid-Open No. 2003-17782P and Japanese Patent Laid-Open No. 2006-196612).
Spin injection memory employs a phenomenon in which the magnetized state of a magnetic substance changes by interaction between a spin-polarized conduction electron injected into the magnetic substance and electron spin responsible for the magnetization of the magnetic substance.
A description will be made about a tunnel magnetoresistance element (hereinafter TMR) which is a memory element.
The tunnel magnetoresistance element TMR basically has a layered structure which includes two magnetic substance layers separated by a tunnel barrier layer 101 as illustrated in FIG. 1.
One of the magnetic substance layers is a fixed magnetization layer 102 designed so that the magnetized condition remains unchanged. The other magnetic substance layer is a free magnetization layer 103 designed so that a stable magnetized state is obtained in the direction parallel or non-parallel to the magnetization direction of the fixed magnetization layer 102.
A laminated film having two magnetic substance layers (fixed magnetization layer 102 and free magnetization layer 103) exhibits a magnetoresistance effect (MR effect) which causes a change in conductance according to the angle formed between the magnetization directions of the two layers. Stored data is read by applying a voltage across two terminals of this laminate so that a current is output. The magnitude of the output current depends upon the resistance which varies according to the magnetization direction of the free magnetization layer 103 due to the MR effect. The MR effect produced by a tunnel current flowing through the tunnel magnetoresistance element TMR is referred to as the TMR effect.
FIG. 2 illustrates a cell configuration in a spin injection memory using the tunnel magnetoresistance element TMR. FIG. 3 illustrates an equivalent circuit diagram of a memory cell.
A diagrammatically illustrated memory cell MC has the tunnel magnetoresistance element TMR and a select transistor ST.
One end of the tunnel magnetoresistance element TMR is connected to a bit line BL, and the other end thereof to the drain of the select transistor ST. The source of the select transistor ST is connected to a source line SL, and the gate thereof to a word line WL.
Next, a description will be made about electrical characteristics of the tunnel magnetoresistance element TMR.
In the tunnel magnetoresistance element TMR, a tunnel current flow produces a magnetization switching (referred to as spin injection magnetization switching). This leads to a change in electrical memory characteristic, namely, resistance hysteresis characteristic.
FIG. 4 illustrates a current vs voltage characteristic (hysteresis characteristic) of the tunnel magnetoresistance element TMR. Referring to FIG. 1, the direction of current flow from the fixed magnetization layer 102 to the free magnetization layer 103 is the positive direction of cell current in FIG. 4. A cell-applied voltage along the horizontal axis in FIG. 4 gives a positive or negative voltage to the fixed magnetization layer 102 relative to the potential of the free magnetization layer 103.
The electrical characteristic illustrated exhibits the low resistance state with a relatively large slope after crossing the zero current and the high resistance state with a relatively small slope after crossing the zero current. If the cell-applied voltage is increased in the low resistance state, a state change (transition to high resistance) takes place as shown by an arrow Ah in FIG. 4, for example, when the cell-applied voltage is between 0.5 and 1.0 V. On the other hand, if the cell-applied voltage is reduced in the high resistance state, another state change (transition to low resistance) takes place as shown by an arrow Al in FIG. 4, for example, when the cell-applied voltage is between −0.5 and −1.0 V.
The cell operation is controlled to bring about a transition to the high resistance state by setting the cell-applied voltage to 1.0 V and a transition to the low resistance state by setting the cell-applied voltage to −1.0 V.
It is clear that if, based on the above electrical characteristic, the two states are associated with binary data, it is possible to write data to the memory because data inversion is possible. More specifically, data “0” can be written (Write0) by setting the cell-applied voltage to 1.0 V. Conversely, data “1” can be written (Write1) by setting the cell-applied voltage to −1.0 V.
In the memory read operation, a potential of about 0.3 V is, for example, applied to the memory cell to achieve a substantially high magnetoresistance ratio (MR ratio). At this time, the resistance of the tunnel magnetoresistance element TMR varies depending on the write state. Therefore, it is possible to determine whether the TMR is in the high resistance state (data “0” being written) or low resistance state (data “1” being written) by reading the resistance value.
Although the above description applies to a case where the read operation is performed on the Write0 (transition to high resistance) side, the read operation is also possible on the Write1 (transition to low resistance) side, for example, by applying a voltage of about −0.3 V to the memory cell.
At this time, the larger the difference between read resistance values, the easier it is to discriminate between data “0” and data “1.” Therefore, the larger the absolute value of the voltage applied to the cell during write operation (read voltage), the better. However, increasing the absolute value of the read voltage may make it difficult to provide for a margin of a transition voltage capable of producing a state transition, possibly resulting in erroneous write of a memory cell connected to the same bit line (read disturb). To prevent a read disturb, the cell-applied voltage must be controlled with precision during read operation. Further, if the MR ratio has a dependence on cell-applied voltage, the optimal MR ratio must be achieved before proceeding with read operation.
Under these circumstances, a technique is known which produces a sense amplifier reference voltage from a memory cell having the tunnel magnetoresistance element TMR (or reference cell) in order to secure a read disturb margin (e.g., Japanese Patent Laid-Open No. 2002-197853, hereinafter referred to as Patent Document 3).
In Patent Document 3, the cell-applied voltage is controlled by inserting a voltage gate transistor (V-gate Tr. (NMOS)) between a sense node and a bit line. This transistor functions as voltage control means to cause a voltage drop. Then, a bit line voltage applied to the cell is controlled by setting the gate voltage of the voltage gate transistor to VBIAS (intermediate voltage between Vdd and GND potential).
FIG. 5 illustrates part of a column circuit to which the technique of the above Patent Document 3, for example, is applicable.
In the diagrammatically illustrated column circuit, the memory cell MC with an MR element is connected between the source line SL maintained at the GND potential and the bit line BL. Further, a voltage gate transistor Mn (V-gate Tr. (NMOS)) is connected between the bit line BL and the supply line of a source voltage Vdd. Although not specifically illustrated, a voltage generating circuit adapted to generate a reference voltage is connected to the gate of the voltage gate transistor Mn. The voltage generating circuit has a reference cell which models after the memory cell and has half the MR ratio of the memory cell. This circuit is used to generate VBIAS which is applied to the gate of the voltage gate transistor Mn.
This column circuit is provided for each column of a memory cell array. Two types of column circuits are formed adjacent to each other as a pair, one column circuit to which VBIAS is applied and another in which voltage is not so much controlled by the voltage gate transistor. A sense amplifier is connected between the bit lines of the two column circuits to perform a read operation.
As an example of canceling the impact of variation in characteristics of the transistor which functions as a switch to apply a voltage to a bit line, there is a method of controlling the transistor gate voltage using a negative feedback amplifier (e.g., Japanese Patent Laid-Open No. 2004-103212 and Japanese Patent Laid-Open No. 2003-529879, hereinafter referred to as Patent Documents 4 and 5).
FIG. 6 illustrates the schematic configuration given in the Patent Document 4.
In the diagrammatically illustrated circuit, the memory cell MC with the MR element is connected between the source line SL maintained at the GND potential and the bit line BL. Further, the NMOS transistor Mn (V-gate Tr.) and a current source IS are connected between the bit line BL and the supply line of the source voltage Vdd.
The output of a negative feedback amplifier NFA is connected to the gate of the NMOS transistor Mn. The inverted input “−” of the negative feedback amplifier NFA is connected to the source of the NMOS transistor Mn, whereas a potential Vmtj is applied to the non-inverted input “+” thereof.
This configuration makes it possible to maintain the source of the NMOS transistor Mn at a constant voltage irrespective of variation in characteristics of the transistor Mn.